`timescale 10fs/1fs
module TEST_ALU;
	reg [31:0] x,y;
	reg [2:0] alu;
	
	wire [31:0] z;
	wire zero;
	
	ALU U0(.*);

	initial fork
	#0 x<=32'b0100;
	#0 y<=32'b0101;
	#0 alu<= 3'b000;
	#1 alu<= 3'b001;
	#2 alu<= 3'b010;
	#3 alu<= 3'b110;
	#4 alu<= 3'b111;
	
	#10 x<=32'b11;
	#10 y<=-32'b1010;
	#10 alu<= 3'b000;
	#11 alu<= 3'b001;
	#12 alu<= 3'b010;
	#13 alu<= 3'b110;
	#14 alu<= 3'b111;
	join

endmodule